MIL-PRF-19500/548H
4.4.2.2 Group B inspection, table E-VIb (JAN, JANTX, and JANTXV) of MIL-PRF-19500.
Subgroup
Method
Condition
B2
1056
Thermal shock: Test condition B (25 cycles). Total test time = 72 hours maximum.
B2
1071
Fine leak - condition G or H, gross leak - condition C.
High temperature isolation voltage test conditions: VISO = 150 V dc (see 4.5.2),
B3
TA = +125°C, t = 24 hours minimum. n = 22, c = 0, small lot sample size = 8, c = 0.
B3
1027
IF = 20 mA dc, PT = 275 ± 25 mW at TA = +25°C ±3°C (see figure 4). No heat sink
or forced air cooling directly on the device shall be permitted.
B4
2037
Test condition A.
B5, B6
Not applicable.
4.4.3 Group C inspection. Group C inspection shall be conducted in accordance with the conditions specified for
subgroup testing in table E-VII of MIL-PRF-19500. Electrical measurements (end-points) and delta requirements
shall be in accordance with table I, subgroup II herein. Samples for group C testing of JAN, JANTX, and JANTXV
devices processed through Group A alternate flow shall be randomly selected from all appropriate part numbers
represented in the inspection lot.
Subgroup
Method Condition
C2
1056
Thermal shock: Test condition A.
C2
2036
Terminal strength, test condition E. Not applicable to surface mount devices.
C2
1071
Fine leak - condition G or H; gross leak - condition C.
C3
2016
Non-operating; 1,500 G, t = 0.5 ms, 5 blows in each orientation: X1, Y1, Z1
C3
2056
50 G minimum. Non-operating.
C3
2006
Non-operating, 30,000 G, X1, Y1, Z1 orientations.
C6
1026
IF = 20 mA dc, PT = 275 ±25 mW at TA = +25°C ±3°C, T = 1,000 hours (see figure 4).
No heat sink or forced air cooling directly on the device shall be permitted.
4.4.4 Group E inspection. Group E inspection shall be conducted in accordance with MIL-PRF-19500 and table II
herein.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows:
4.5.1 Pulse measurements. Conditions of pulse measurements shall be as specified in MIL-STD-750.
4.5.2 High temperature isolation voltage lot verification. This test shall be performed by shorting both the anode
and cathode terminals of the LED (light emitting diode) and shorting together the collector, emitter, and base
terminals of the transistor. The sample shall be split into two approximately equal groups and the specified VISO
applied between the LED terminals (positive) and transistor terminals (negative) of one group. The specified isolation
voltage shall be repeated with the LED terminals (negative) and the transistor terminal (positive) for the remaining
group. All voltages shall be applied at the specified ambient temperature.
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