MIL-PRF-19500/486H
4.5.2 High temperature isolation voltage lot verification. This test shall be performed by shorting both the anode
and cathode terminals of the LED (light emitting diode) and shorting together the collector, emitter, and base
terminals of the transistor. The sample shall be split into two approximately equal groups and the specified VISO
applied between the LED terminals (positive) and transistor terminals (negative) of one group. The specified isolation
voltage shall be repeated with the LED terminals (negative) and the transistor terminal (positive) for the remaining
group. All voltages shall be applied at the specified ambient temperature.
4.5.3 Input LED tests. These tests shall be performed with the output transistor terminals open.
4.5.4 Output transistor tests. These tests shall be performed with the input LED terminals open.
4.5.5 Isolation and coupling capacitance tests. These tests shall be performed in both polarities between both
input terminals 5 and 7 shorted together and the output terminals 1, 2, and 3 shorted together (see figure 1) or input
terminals 1 and 6 shorted together and output terminals 3, 4, and 5 shorted together (see figure 2).
* 4.5.6 On-state collector current, phototransistor mode. These tests shall be performed with the base open in the
circuit, with the active area of the phototransistor tied to the base and the LED biased on to emit light, to provide bias
to the base.
4.6 Internal visual (pre-cap) inspection (JANTXV and JANS only). Internal visual inspection shall be performed in
accordance with methods 2072 and 2073 of MIL-STD-750, and as specified herein. Method 2072 shall be used for
inspecting transistor die and completed assembly. Method 2073 shall be used for inspecting light emitting diode.
4.6.1 Gallium arsenide or gallium aluminum arsenide light emitting diode die inspection. The die shall be
inspected under 100X magnification.
4.6.2 Silicon phototransistor visual inspection. The die shall be inspected under 100X magnification.
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